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NVIDIA

ASIC Verification Engineer - SOC Clocks Methodology

Posted Yesterday
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Bengaluru, Bengaluru Urban, Karnataka
Junior
Bengaluru, Bengaluru Urban, Karnataka
Junior
The ASIC Verification Engineer will work within the Hardware SOC Clocking team to develop and redefine methodologies for high-quality system level IP design and verification. Responsibilities include designing and building test benches and flows using Python, System Verilog, and UVM, collaborating with architects and engineers, and ensuring robust verification at various levels.
The summary above was generated by AI

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing.

Today, our GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can take on, and that matter to the world. The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible for our environment. The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Verification Engineer, who has a real passion for verification methodologies and implementation that enable high-quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC).

What you'll be doing:

  • Be an integral part of the Hardware SOC Clocking team, re-defining and developing Methodologies that make the industry's leading SOCs.

  • Develop innovative methodologies that are scalable and re-usable to verify the micro-architecture and design.

  • Design and build new test benches and Flows in Python, System Verilog , UVM.

  • Work with architects, designers, and SW engineers to accomplish your tasks.

What we need to see:

  • Masters or Bachelor's Degree in VLSI or Electronics Engineering with 1+ years of relevant industry experience.

  • Strong coding skills in Python or other industry-standard scripting languages.

  • Exposure to various Designs and Verification Flows at different testbenches.

  • Excellent debugging and analytical skills.

  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools )

  • Good understanding of RTL design (Verilog).

  • Experience in crafting test bench environments for unit and system-level verification.

  • Experience in UVM is a plus.

  • Great communication and teamwork skills to interact within the team and with cross-functional teams.

With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!

Top Skills

Python
System Verilog

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