Leads end-to-end power, performance, and area optimization for AI semiconductor SoCs. Influences architecture, RTL, memory hierarchies, dataflows, floorplanning, multi-voltage domains, synthesis, placement, clock-tree synthesis, routing, and power-analysis workflows. Partners with architecture, RTL, physical design, EDA vendors, and software teams to develop custom methodologies and deliver energy-efficient silicon under stringent PPA constraints.
Power Architect – AI SOC
Location: Bangalore Hybrid/ Remote
About EnCharge AI
EnCharge AI is building the next generation AI platform. Our novel in-memory-computing architecture delivers a 10x step-function improvement in compute energy efficiency and performance for AI inference workloads. As the demands of artificial intelligence move beyond today's models, we believe fundamental underlying infrastructure must evolve. We are an experienced team of AI researchers, silicon & systems engineers, and architects backed by leading investors, poised to become the essential platform for the next wave of AI innovation.
Role Overview:
We are seeking a critical-thinking, highly collaborative Power Architect to drive end-to-end PPA (Power, Performance, Area) excellence for our next-generation AI semiconductor chips. In this cross-functional IC role, you will bridge the gap between front-end conceptualization and back-end implementation, influencing SoC architecture, RTL design, and physical layout to deliver industry-leading power efficiency for complex AI workloads.
Key Responsibilities:
- Architectural Influence: Drive comprehensive SoC-level power and thermal management architecture. Influence microarchitecture, memory hierarchies, and dataflows to minimize dynamic and leakage power for AI inference and training workloads.
- RTL & Floorplan Guidance: Review and guide RTL implementation to ensure consistency with power and timing goals. Collaborate directly with Physical Design (PD) teams to refine area constraints, floorplanning, and multi-voltage domain structures.
- PD Recipe Engineering: Develop, fine-tune, and build advanced Physical Design recipes (covering synthesis, placement, clock tree synthesis, and routing) specifically tailored to achieve best-in-class PPA targets.
- EDA & Custom Solutions: Partner with EDA vendors and internal teams to drive the adoption and customization of advanced power analysis tools (e.g., PowerArtist, PrimePower, Joules). Develop custom scripts and design workflows where standard tools fall short to squeeze out every milliwatt of power savings.
- Cross-Functional Collaboration: Lead PPA analysis and trade-off discussions across RTL, architecture, and PD teams. Act as the central hub to resolve complex bottlenecks and ensure the final silicon meets strict power budgets.
Who You Are:
- A Critical Thinker: You look beyond block-level metrics to understand how early architectural choices impact the final silicon's physical layout and thermal limits.
- A Master Collaborator: You excel at breaking down silos, bringing together hardware, physical design, and software/firmware teams to achieve a unified PPA goal.
- An Innovator: You aren't satisfied with default EDA flows and actively build custom methodologies to push the boundaries of chip efficiency.
Qualifications:
- BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
- 12+ years of semiconductor experience with a deep focus on SoC architecture, low-power RTL design, and Physical Design (PD) implementation.
- Proven track record of delivering complex, high-performance silicon (AI accelerators, GPUs, or advanced SoCs) under stringent PPA constraints.
- Hands-on expertise with power intent (UPF/CPF) and industry-standard power estimation/analysis tools.
- Strong scripting and automation skills (Python, Tcl, Perl) for customizing EDA tool flows and PPA data analysis.
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