The Principal Design Engineer will develop performance models for DDR memory controller architectures, analyze trade-offs, automate performance metrics generation, and collaborate with Memory Architects. A strong foundation in hardware modeling and performance principles is required.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Performance Modeling Engineer
Location – India (Pune)
Summary
We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.
Responsibilities
- Develop cycle-level performance models in SystemC or C++
- Correlate performance models to match RTL configurations and traffic conditions
- Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
- Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
- Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
- Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks
Required Skills
- BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
- 8+ years of experience in hardware modeling, functional or performance
- Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
- Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
Additional Skills
- Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
- Understand memory protocols and timing – DDR4, DDR5, LP4, LP5
- Experience using performance simulators – Memory Controller, NoC, CPU models
- Coding in Python and familiarity with packages like Pandas, Matplotlib
- Experience working with performance benchmarks – SPEC, STREAM, etc
- Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies
We’re doing work that matters. Help us solve what others can’t.
Top Skills
C++
Python
Systemc
Similar Jobs
Be an Early Applicant
The Principal Design Engineer is responsible for design verification of interconnect IP, including crafting and executing verification plans, coverage collection, and collaborating with cross-functional teams. The role demands strong technical skills and experience in design verification along with knowledge of interconnects and related programming languages.
Be an Early Applicant
The Principal Design Engineer is responsible for the integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems. This role involves resolving complex implementation issues, supporting integration reviews, performing simulations for functionality, and enhancing customer communication and experience.
Be an Early Applicant
The Technical Lead will develop scalable web applications using Angular, mentor junior staff, lead technical teams, and implement best practices. Responsibilities include application design, management of mono repos with NX, and developing robust architectures while ensuring code quality and team collaboration in Agile methodologies.
What you need to know about the Chennai Tech Scene
To locals, it's no secret that South India is leading the charge in big data infrastructure. While the environmental impact of data centers has long been a concern, emerging hubs like Chennai are favored by companies seeking ready access to renewable energy resources, which provide more sustainable and cost-effective solutions. As a result, Chennai, along with neighboring Bengaluru and Hyderabad, is poised for significant growth, with a projected 65 percent increase in data center capacity over the next decade.
