Lead clock architecture and physical implementation for advanced SoC designs, including clock tree synthesis, SPICE analysis, timing closure, power optimization, clocking IP integration, and methodology development. Collaborate with architecture, RTL, physical design, STA, verification, and sign-off teams. Use industry-standard EDA tools and scripting languages to automate flows, analyze timing data, and ensure predictable silicon implementation from RTL through GDSII.
SoC Clocking Specialist (Physical Design)
Location: Bengaluru, India
Role Type: Full-time
About the Role
We are looking for a highly skilled SoC Clocking Specialist to lead the clock architecture and physical implementation of our next-generation edge AI hardware. In this critical role, you will bridge the gap between frontend logic and backend execution, partnering directly with Architecture, RTL, and Timing teams to architect, implement, and sign-off a highly robust and power-efficient clock tree on advanced technology nodes.
Key Responsibilities
- Cross-Functional Coordination: Collaborate closely with the SoC Architecture and RTL teams to define optimal clocking schemes, clock gating strategies, and synchronous/asynchronous boundaries.
- Clock Tree Implementation: Own the end-to-end Clock Tree Synthesis (CTS) strategy, working alongside the Physical Design and Static Timing Analysis (STA) teams to drive timing closure, minimize skew, and optimize insertion delay.
- SPICE Simulation & Analysis: Run detailed SPICE simulations (using HSPICE, CustomSim, etc.) on critical clock paths to accurately model and analyze jitter, duty cycle distortion, slew degradation, and local on-chip variation (OCV).
- Power & Performance Optimization: Architect custom clock distribution networks (trees, meshes, or hybrid topologies) that meet stringent high-frequency requirements while strictly managing dynamic power—a critical factor for edge AI silicon.
- IP Integration: Integrate and validate high-speed clocking IPs (PLLs, DLLs, oscillators) into the top-level SoC clock network.
- Methodology Development: Establish and refine CTS and SPICE analysis methodologies to ensure silicon predictability from RTL to GDSII.
Qualifications & Skills
- Education & Experience: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI Design, or a related field, with 8+ years of experience in semiconductor physical design, with a strong focus on clocking architecture and implementation.
- Technical Expertise:
- Deep understanding of high-performance clock tree methodologies across advanced process nodes.
- Proven hands-on experience running and analyzing SPICE simulations for clock networks.
- Thorough understanding of STA constraints, jitter budgeting, cross-talk, and variation modeling.
- EDA Tool Proficiency: Strong command over industry-standard EDA tools for physical design and timing (e.g., Synopsys ICC2/PrimeTime or Cadence Innovus/Tempus) and circuit simulation.
- Collaboration & Problem Solving: Exceptional communication skills with a proven ability to align cross-functional teams (Frontend, Design Verification, PD, and Sign-off) around complex technical solutions.
- Scripting/Automation: Proficiency in Python, Tcl, or Perl to automate flows and analyze large timing datasets.
What We Offer
- The opportunity to be part of a ground-up silicon engineering team in India.
- Meaningful impact on the architecture and execution of cutting-edge AI hardware.
- A collaborative environment focused on engineering excellence and innovation.
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