Jobs at Microchip Technology Inc.

Lead block-level verification: create test plans, develop UVM/SystemVerilog testbenches, integrate with RTL, run regressions, analyze functional/code coverage, and work with design teams to debug and close issues.

Develop, test, and troubleshoot embedded firmware for secure Platform Root Of Trust products. Onboard and support customers, deliver technical demos, resolve issues via Salesforce, perform hardware and system integration testing, and produce application notes while collaborating with multi-site cross-functional teams.

Design and develop web and desktop applications using modern tools. Collaborate with global teams to provide technical solutions, mentor engineers, participate in design discussions and code reviews, and own high-quality software deliverables.

Design and layout IC package routing and substrates for high-speed mixed-signal products. Perform PCB breakout and BGA fanout studies, create APD design rules and routing constraints, collaborate with signal integrity and reliability teams, oversee external designers, produce routing reports, and manage package design schedules to ensure manufacturability.

Perform block- and full-chip DFT for ASIC/SoC designs including boundary-scan, memory BIST, scan insertion with compression, ATPG and pattern verification, gate-level simulation, silicon bring-up and failure debug on ATE, and collaborate with RTL/STA teams to resolve timing and DFT DRC issues.

Senior DevOps engineer responsible for designing and operating CI/CD pipelines, automating infrastructure with IaC (Terraform/CloudFormation), containerizing and orchestrating applications with Docker and Kubernetes, monitoring systems, optimizing cloud costs, enforcing security and compliance, and deploying AI/LLM tooling into Kubernetes clusters while collaborating across teams.

Design and execute block-level verification for RTL using SystemVerilog and UVM. Develop test plans and testbenches, create and run regression tests, analyze code and functional coverage, integrate with RTL, and collaborate with design teams to debug and resolve issues.

Lead chip-level design and verification for Touch Controller IPs, from specification and architecture through RTL implementation and verification. Contribute to design reviews, documentation, development methodology, project coordination, and cross-functional collaboration.

Lead full-chip and large block physical design from RTL to GDSII across advanced nodes (40nm to 3nm+). Responsibilities include floorplanning, place-and-route, CTS, timing closure, physical verification, IR/EM checks, IP integration, mentoring junior engineers, and using metric-driven flows to achieve first-pass silicon.

Evaluate and optimize clustered HPC systems, support end users on simulations and best practices, design and maintain software and scripts for driving and monitoring EDA workloads, document HPC infrastructure and workflows, research new technologies, and collaborate with engineering teams to ensure secure, stable, and optimized HPC operations.

Operate, evaluate, and optimize clustered HPC systems for EDA workloads. Provide technical support and best practices to users, design and maintain software/tools to drive and monitor jobs, document HPC/EDA workflows, research new technologies, and collaborate with engineering teams to ensure secure, stable, and high-performance HPC operations.

Develop and maintain automated test frameworks and workflow automation for Microchip development tools and debuggers. Validate debugging tools and embedded applications, create and execute test plans, and contribute as an individual contributor while leading projects when required.

The role involves verifying analog mixed signal systems for microcontrollers and wireless products through simulations and analysis.

Lead the HMID Design team, manage chip-level design processes, collaborate across teams, and contribute to IP specification and verification.

The Senior Verification Engineer will design, verify, and implement complex digital logic solutions, focusing on ARM-based SoCs. Responsibilities include creating test plans, developing testing environments, debugging, and mentoring junior engineers while improving methodologies.

The Senior Application Engineer will develop, test embedded firmware for Secure Computing products, assist customers, and manage technical demos and support.

The Physical Design Engineer will take ownership of implementing RTL2GDSII for large SOCs, involving floor-planning, place-and-route, timing closure, and physical verification checks.

Develop and test embedded firmware for NCS products, collaborating with teams, and contributing to all phases of product lifecycle.

Verify and validate embedded and library software for automotive and embedded ICs. Build and maintain PC and embedded test infrastructures, implement automated tests, execute unit/integration/system verification, document results, perform debugging and defect tracking, collaborate with cross-functional teams, and support performance, reliability, and customer issue resolution.

Develop, implement, and maintain PC-based and embedded test infrastructures and automated software tests. Execute verification at unit, integration, and system levels, perform debugging and failure analysis, document results, and collaborate with software, systems, hardware, and validation teams to improve performance and reliability and support customer issues.