Senior Engineer II – Design

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Job Description:

Join Microchip’s AES Automation Team as a hands-on Senior Engineer, focused on early-stage digital design implementation ("shift-left") activities. You will lead process innovation and partner with design and physical implementation teams to help achieve better power, performance, and area (PPA) and accelerate time-to-market (TTM). In this role, you’ll take ownership of key backend design activities at the front end of the development cycle—helping to identify and resolve issues sooner, and enabling designers to focus on core design work.

You’ll collaborate with RTL design teams, implementation engineers, physical design, and DFT engineers to perform trial synthesis, RTL linting, DFT RTL hookup, SDC (timing constraint) creation and review, power estimation and checklist management. You’ll also mentor team members, help define and document best practices, and play a key role in evolving our shift-left design flows for maximum efficiency and quality.

Key Responsibilities

• Take ownership of early-stage backend design tasks for assigned blocks, including DFT RTL hookup, RTL QA (structural and design rule checks), SDC (timing constraints) creation and review, power estimation, and signoff checklist management.
• Perform trial synthesis to identify and address design issues early.
• Review static timing analysis (STA) results, warnings, and complete checklists on behalf of the design team, providing technical guidance and recommendations.
• Collaborate with RTL designers, physical design, and DFT teams to ensure early detection and resolution of issues related to synthesis, constraints, and timing.
• Mentor and train team members on early-stage implementation flows, tools, and best practices.
• Document lessons learned, process improvements, and recommendations for future projects.
• Proactively identify opportunities to improve efficiency, parallelize work, and offload designers.
• Communicate clearly and effectively with global teams (including regular online meetings and written updates).

Requirements/Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of digital design, including RTL (SystemVerilog), trial synthesis, and SDC constraints.
• Strong scripting skills (Python, TCL, shell, Perl).
• Experience with EDA tools such as Genus, Conformal LEC/CLP, Spyglass CDC, Joules, HAL, Fishtail, or similar.
• Demonstrated ability to take ownership of technical challenges and drive them to completion.
• Excellent communication skills, with the ability to collaborate across time zones and cultures.
• Willingness to mentor and train others, and to help define and document new processes.
• High intelligence, initiative, and a proactive, problem-solving mindset.

Preferred Qualifications

• Experience with flow/process improvement, or “shift-left” methodologies.
• Familiarity with DFT, and logic equivalence checking (LEC).
• Familiarity with power estimation with vectors, and UPF (unified power format).
• Familiarity with additional EDA tools.
• Prior experience mentoring or training engineers.

About the AES Automation Team

The AES Automation Team is part of Microchip’s Advanced Engineering Services (AES) organization, focused on flow improvement, technical advising, and driving PPA and TTM across digital design and physical implementation teams. We partner closely with product design and CAD groups to deliver best-in-class silicon solutions. Our shift-left initiative is a strategic focus, enabling earlier risk reduction and faster time-to-market for our next-generation products.

Travel Time:

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