This role is for one of Weekday’s clients
Salary range: Rs 1000000 - Rs 1400000 (ie INR 10-14 LPA)
Min Experience: 4+ years
Location: Bengaluru, Hyderabad, Telangana, India, Tamil Nadu, India
JobType: full-time
We are seeking an experienced Verification Engineer – GPM Subsystem with 4+ years of hands-on experience in digital design verification and a strong background in SystemVerilog and UVM. The role will focus on verification of GPU Power Management (GPM) subsystems, developing robust verification environments, driving functional coverage, and ensuring high-quality verification closure through tapeout.
The ideal candidate will have practical experience working on GPU subsystem verification and be comfortable building and maintaining UVM-based testbenches, developing verification strategies, debugging complex failures, and collaborating closely with RTL and design teams.
RequirementsKey Responsibilities
- Develop, enhance, and maintain UVM-based verification environments for GPU Power Management subsystems.
- Develop comprehensive verification and test plans based on design specifications and functional requirements.
- Write and maintain SystemVerilog testbenches, sequences, drivers, monitors, scoreboards, and coverage components.
- Develop functional coverage models to ensure comprehensive verification of GPM functionality and corner cases.
- Write and implement SystemVerilog Assertions (SVA) for protocol, functional, and design-level checks.
- Create and execute constrained-random and directed test scenarios.
- Perform detailed simulation debug, root-cause analysis, and failure resolution.
- Collaborate with RTL designers and other verification engineers to identify, reproduce, and resolve design issues.
- Track verification progress, coverage metrics, bugs, and closure activities.
- Drive verification closure to meet tapeout-quality standards.
- Validate subsystem interactions and ensure robust operation across different power-management scenarios.
- Contribute to improving verification methodologies, automation, and reusable verification components.
- 4+ years of hands-on experience in ASIC/SoC functional verification.
- Strong proficiency in SystemVerilog.
- Strong hands-on experience with UVM and UVM-based verification environments.
- Proven experience verifying GPU subsystems, with specific experience in GPM / GPU Power Management preferred.
- Experience developing verification and test plans.
- Strong understanding of functional coverage and coverage-driven verification.
- Hands-on experience developing and debugging SVA.
- Strong simulation and debugging skills with the ability to drive issues through verification closure.
- Familiarity with valid-ready or similar handshake-based protocols.
- Experience working through complete verification cycles up to tapeout.
- Experience with RTL design and debugging.
- Knowledge of GPU architecture and GPU subsystems.
- Experience with AXI or other standard on-chip protocols.
- Exposure to LPDDR or HBM memory interfaces.
- Experience with power-management architectures and low-power design concepts.
- Familiarity with semiconductor verification flows, regressions, coverage analysis, and signoff processes.
- B.E./B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related technical discipline.
The ideal candidate is a hands-on verification professional with strong SystemVerilog and UVM expertise and practical experience working on complex GPU or semiconductor subsystems. You should be comfortable taking ownership of verification activities from test planning and environment development through coverage closure and tapeout.
Strong debugging ability, attention to detail, and effective collaboration with RTL and design teams are essential for success in this role.
Success MetricsSuccess will be measured through comprehensive functional coverage, verification quality, timely closure of bugs and coverage gaps, robustness of the UVM environment, effectiveness of debug and root-cause analysis, and successful achievement of tapeout-quality verification closure.
