Jobs at Cisco

Leads finance for Cisco Capital APJC, supporting over $1 billion in annual bookings. Partners with sales and cross-functional leaders on deal structuring, financial modeling, forecasting, profitability, credit risk, and business planning. Manages and develops a team of three finance professionals while advising senior leadership and driving regional financial performance.

Leads technical customer success for Splunk security and core platform products. Provides architecture, implementation, configuration, optimization, onboarding, enablement, health remediation, security use-case activation, and strategic consulting. Advises customers and account teams on Splunk Enterprise Security, UBA/UEBA, SOAR, data onboarding, risk analytics, and platform adoption while resolving complex technical challenges and improving customer value realization.

Lead implementation and integration of hardware Design-for-Test features supporting ATE, in-system testing, debug, diagnostics, and post-silicon validation. Develop reusable DFT IP and test strategies for advanced silicon, bare-die, and stacked-die designs. Collaborate with design, verification, physical design, and validation teams on RTL integration, ATPG, scan, JTAG, BIST, timing validation, gate-level simulation, and test logic debugging.

Implement and integrate ASIC hardware design-for-test features supporting ATE, in-system testing, debug, and diagnostics. Develop reusable DFT IP and test strategies for advanced silicon designs, including bare and stacked die. Collaborate with design, verification, physical design, and post-silicon teams to validate test logic throughout implementation and silicon validation. Debug gate-level simulations, validate test timing, and support ATPG, scan, BIST, JTAG, and memory BIST architectures with minimal mentorship.

Implement and integrate hardware Design-for-Test features supporting ATE, in-system testing, debug, diagnostics, and post-silicon validation. Develop reusable DFT IP and test strategies, collaborate with design, verification, physical design, and integration teams, and validate test logic throughout implementation. Responsibilities include JTAG, scan, BIST, ATPG, gate-level simulation, timing validation, ATE pattern work, and silicon debug. The role requires independent problem-solving and scripting capabilities.

Lead design-for-test (DFT) for advanced ASICs: define and implement DFT/IP, collaborate with RTL and physical teams, drive ATPG/AT E and post-silicon validation, debug test logic, and integrate testability throughout implementation and validation flows.

Drive quota attainment for MNC accounts in South India by qualifying and managing partner-generated opportunities, collaborating with partners and architecture teams, maintaining pipeline hygiene, and aligning Cisco solutions to customer needs.

Support and manage technical manufacturing challenges with contract manufacturing partners for telecom equipment. Plan production layouts and capacity, debug process and yield issues, drive corrective actions and cost reductions, manage quality metrics and audits, oversee site budgeting, and mentor junior team members.