Teams at N Human Resources & Management Systems

Own DFT architecture and implementation from RTL through tapeout, including scan insertion, ATPG, MBIST/LBIST, boundary scan, compression, test point insertion, and fault coverage analysis. Debug silicon test failures, correlate results with simulations, and drive testability closure with RTL, physical design, and STA teams. Lead and mentor a team of 3–4 DFT engineers.

Senior Sales Manager responsible for growing semiconductor business across key accounts. Owns the full B2B sales cycle, revenue targets, pipeline development, account strategy, negotiations, and client relationships with semiconductor companies and technical decision-makers. Collaborates with technical and delivery teams, monitors market trends, and mentors a team of 3–4 sales and business development executives.

Performs VLSI physical design from RTL handoff through tapeout, including floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, physical verification, DRC/LVS cleanup, ECO implementation, and signoff. Collaborates with STA, DFT, and RTL teams on block-level closure and supports full-chip integration.