Jobs at N Human Resources & Management Systems

Own DFT architecture and implementation from RTL through tapeout, including scan insertion, ATPG, MBIST/LBIST, boundary scan, compression, test point insertion, and fault coverage analysis. Debug silicon test failures, correlate results with simulations, and drive testability closure with RTL, physical design, and STA teams. Lead and mentor a team of 3–4 DFT engineers.

Senior Sales Manager responsible for growing semiconductor business across key accounts. Owns the full B2B sales cycle, revenue targets, pipeline development, account strategy, negotiations, and client relationships with semiconductor companies and technical decision-makers. Collaborates with technical and delivery teams, monitors market trends, and mentors a team of 3–4 sales and business development executives.

Performs VLSI physical design from RTL handoff through tapeout, including floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, physical verification, DRC/LVS cleanup, ECO implementation, and signoff. Collaborates with STA, DFT, and RTL teams on block-level closure and supports full-chip integration.

Own functional verification for design blocks and subsystems through silicon-quality signoff. Develop UVM environments, testbenches, test plans, constrained-random tests, coverage models, assertions, and formal verification. Debug RTL and testbench issues, drive coverage and bug closure, maintain regression health, collaborate with design and architecture teams, and mentor 3–4 verification engineers.

Own synthesis and static timing analysis across VLSI design blocks, driving timing signoff from RTL through tapeout. Responsibilities include logic-aware synthesis, equivalence checks, VCLP signoff, SDC and UPF constraint development, timing closure across design stages and corners, manual ECOs for timing and DRC violations, and full-chip timing closure. The role also leads and mentors 4–5 engineers while partnering with RTL and physical design teams on SoC timing.

Lead full-chip and block-level physical design, including floorplanning, placement, CTS, routing, timing, power, signal-integrity, and physical verification signoff. Drive advanced-node tapeouts, resolve timing and congestion issues, collaborate with CAD, methodology, and IP teams, and mentor junior engineers.

Drive B2B field sales across Chennai through lead generation, cold visits, client acquisition, relationship management, and complete sales-cycle ownership. The role requires meeting daily and monthly targets, understanding customer needs, recommending solutions, gathering market feedback, and representing the company as a frontline brand ambassador.