Top Tech Jobs & Startup Jobs in Chennai

Own verification for complex blocks and subsystems within ARM-based SoCs. Develop SystemVerilog and UVM test environments, create test plans and constrained-random tests, manage regressions, analyze code and functional coverage, debug RTL and testbench issues, and collaborate with architects and validation teams. The role also contributes to automation initiatives, methodology improvements, cross-site program leadership, and mentorship of junior engineers.

Design and execute block-level verification for RTL using SystemVerilog and UVM. Develop test plans and testbenches, create and run regression tests, analyze code and functional coverage, integrate with RTL, and collaborate with design teams to debug and resolve issues.

Lead chip-level design and verification for Touch Controller IPs, from specification and architecture through RTL implementation and verification. Contribute to design reviews, documentation, development methodology, project coordination, and cross-functional collaboration.

Design, implement, test, and maintain web pages and portals for Microchip’s Corporate Design Automation team. Collaborate with global stakeholders to understand requirements and deliver web solutions. The role requires strong Python and Django skills, web UI development expertise, relational database knowledge, Linux and Windows experience, and familiarity with AI/ML. Candidates should demonstrate attention to detail, multitasking ability, independence, teamwork, and effective communication.

Develop and test embedded firmware for secure computing products, including platform Root of Trust devices. Support customer onboarding, technical troubleshooting, demos, application notes, and issue resolution through Salesforce. Perform hardware and system integration testing, verification, and validation while collaborating with distributed cross-functional teams. The role requires strong embedded C programming, Python scripting, debugging, security fundamentals, and experience with microcontrollers, microprocessors, ARM architecture, and real-time operating systems.

Lead full-chip and large block physical design from RTL to GDSII across advanced nodes (40nm to 3nm+). Responsibilities include floorplanning, place-and-route, CTS, timing closure, physical verification, IR/EM checks, IP integration, mentoring junior engineers, and using metric-driven flows to achieve first-pass silicon.

Evaluate and optimize clustered HPC systems, support end users on simulations and best practices, design and maintain software and scripts for driving and monitoring EDA workloads, document HPC infrastructure and workflows, research new technologies, and collaborate with engineering teams to ensure secure, stable, and optimized HPC operations.

Senior SDET focused on designing and implementing automated test frameworks and suites for embedded firmware and drivers (primarily USB). Responsibilities include white‑box testing, unit/system/API/end‑to‑end tests, performance and fault‑injection testing, security/vulnerability validation, CI/CD integration, and collaborating across development, product, and QA teams.

Operate, evaluate, and optimize clustered HPC systems for EDA workloads. Provide technical support and best practices to users, design and maintain software/tools to drive and monitor jobs, document HPC/EDA workflows, research new technologies, and collaborate with engineering teams to ensure secure, stable, and high-performance HPC operations.

The role involves verifying analog mixed signal systems for microcontrollers and wireless products through simulations and analysis.